High-level Speciication and Eecient Implementation of Pipelined Circuits

| This paper describes a novel approach to high-level synthesis of arbitrarily complex pipelined circuits, including pipelined circuits with feedback, and the synthesis algorithm that makes the approach viable in practice. Our approach provides a high-level, modular speciication language with an eecient implementation. In our system, the designer speciies the circuit as a set of independent modules connected by conceptually unbounded queues. He also speciies the desired lengths of the queues in the nal implementation. Our synthesis algorithm automatically transforms the modular, asynchronous speciication into a tightly coupled, fully synchronous implementation in synthesizable Verilog.